-- $RCSfile: mult_gen_v11_0_xst_comp.vhd,v $ $Revision: 1.3 $ $Date: 2009/09/08 15:51:09 $
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library ieee;
use ieee.std_logic_1164.all;

package mult_gen_v11_0_xst_comp is

  component mult_gen_v11_0_xst is
    generic (
      C_VERBOSITY         : integer := 0;
      C_MODEL_TYPE        : integer := 0;
      C_XDEVICEFAMILY     : string  := "virtex4";
      C_A_WIDTH           : integer := 18;
      C_A_TYPE            : integer := 0;
      C_B_WIDTH           : integer := 18;
      C_B_TYPE            : integer := 0;
      C_OUT_HIGH          : integer := 35;
      C_OUT_LOW           : integer := 0;
      C_MULT_TYPE         : integer := 1;
      C_OPTIMIZE_GOAL     : integer := 1;
      C_HAS_CE            : integer := 0;
      C_HAS_SCLR          : integer := 0;
      C_CE_OVERRIDES_SCLR : integer := 1;
      C_LATENCY           : integer := -1;
      C_CCM_IMP           : integer := 0;
      C_B_VALUE           : string  := "111111111111111111";
      C_HAS_ZERO_DETECT   : integer := 0;
      C_ROUND_OUTPUT      : integer := 0;
      C_ROUND_PT          : integer := 0);
    port (
      CLK         : in  std_logic                                       := '1';
      A           : in  std_logic_vector(C_A_WIDTH-1 downto 0)          := (others => '0');
      B           : in  std_logic_vector(C_B_WIDTH-1 downto 0)          := (others => '0');
      CE          : in  std_logic                                       := '1';
      SCLR        : in  std_logic                                       := '0';
      ZERO_DETECT : out std_logic_vector(1 downto 0)                    := (others => '0');
      P           : out std_logic_vector(C_OUT_HIGH-C_OUT_LOW downto 0) := (others => '0');
      PCASC       : out std_logic_vector(47 downto 0)                   := (others => '0')); 
  end component;

end mult_gen_v11_0_xst_comp;

